TSMC’s shrinking silicon roadmap could mean big things for your Apple devices

Taiwan Semiconductor Manufacturing Company (TSMC) just held its 2024 North America Technology Symposium, where it filled in attendees and investors on its technology roadmap for the future.

You may rightly ask: okay but what does this have to do with me, a user of Apple products? Well, TSMC is a chip fabrication company, and likely the most advanced one in the world. They’ve been Apple’s partner for nearly all of its chips major chips—the A series for iPhones and iPads, the M series for Macs, and more. And Apple is often first in line for new manufacturing processes from TSMC, paying a premium to be the first customer to get to use 5nm or 3nm technologies, for example.

Here’s a summary of the TSMC roadmap and what it might mean for future Apple silicon, and therefore future iPhones, iPads, Macs, and more.

What’s a nanometer?

Before we talk about TSMC’s future technologies, let’s have a quick reminder on what a “nanometer” is in this context. Technically, it’s one billionth of a meter. A human hair is between 50,000 and 100,000nm thick. Most bacteria are between 1,000 and 10,000 nanometers.

In silicon process technology, the “nanometer” measurement is how big some of the features of the chip are. Different companies measure different features–it used to be the length between the source and drain parts of a field-effect transistor (FET), but these days different parts are measured by different companies.

Apple

Apple

Apple

In other words, 5nm means some specific parts of the chip are only 5 nanometers big, but TSMC’s 5nm is not the same as Intel’s 5nm, is not the same as Samsung’s 5nm, and so on. A smaller nanometer number means you can fit more chip logic or cache or whatever in the same amount of space, which can lead to more powerful chips, lower power consumption, smaller chips that fit into smaller devices, and so on.

Think of it a bit like looking at a city in Apple Maps–zooming out makes everything smaller, putting more buildings, streets, and land on the same amount of screen. That’s what moving to a smaller nanometer process is like more “city” in the same space.

There are many other important aspects of a microprocessor, including the way transistors are insulated, materials used, and so much more, but the “nanometer” measurement has stuck as a way of differentiating one major manufacturing generation from another.

3nm progress

Apple was first with TSMC’s initial 3nm process, which was called N3. The company has now refined that with the N3E process, which is what we think Apple will use in its most advanced products this fall (A18 and M4). While it might seem significant, the main focus of N3E is to make the chips more affordable. There are some slight differences in density and performance but it’s not a major generational change.

TSMC

TSMC

TSMC

2nm coming next year

The next major change is the shift to 2nm, which is expected to happen in 2025. Apple is once again expected to be the first major (and possibly only) customer, so it’s possible that the A19 or other chips (maybe an M5?) that ship in late 2025 will use this process. It all comes down to TSMC’s ability to work out the kinks in manufacturing and yields and such in time to produce tens of millions of chips with it.

Compared to the N3E process, the N2 process is expected to reduce power consumption by 25-30 percent (for a chip of the same complexity and frequency) or to improve performance by 10-15 percent at the same power consumption. Chip density (how much stuff fits into a single area) is expected to increase by 15 percent.

An interesting change to this generation of chips, besides simply being smaller/denser/faster, is something TSMC calls “NanoFlex.” It will allow chip designers to use cells from different chip libraries all on the same wafer. Usually, a chip designer has to use all blocks from a “low power,” “high density,” or “high performance” library, depending on the most important needs of the chip. By letting designs use different parts from different libraries, chips can fine-tune different areas to their needs.

For example, Apple could decide it is most important to make the video and audio encoders and decoders part of the chip as small as possible and lay out that part of the chip using the high-density design libraries while using the energy-efficient libraries for the low-power CPU cores and the high-performance libraries for the performance CPU cores.

For the chips Apple produces, the limiting factor tends to be power and thermal dissipation. So you can probably expect chips made with the N2 process to have more “stuff” in them (cores, cache, bigger and more complex video encoders, etc) to the tune of 15-20 percent, with slightly higher clock speeds and therefore performance, compared to chips from the year before. However, the ability to optimize specific parts of the chip with tools from different chip libraries has the potential to pay off big in terms of higher “peak” performance or lower idle power.

The year after N2 is released, TSMC will have two enhanced versions of the process: N2P which is focused on top performance, and N2X focused on lower voltages and power consumption. It’s unclear whether Apple will adopt one of those for the chips that come in 2026.

A16—we’re doing angstroms now?

The major shift after 2nm (N2) is a process TSMC calls A16 (no relation to the A16 Bionic). It’s a 1.6-nanometer process but now that things are getting so small, they’re sort of getting off “nanometers” and switching to “angstroms.” An angstrom is a ten-billionth of a meter, or 10 times smaller than a nanometer.

This one is not coming until late 2026, almost certainly too late for Apple to use that year. We’ll see chips made with the A16 process from Apple in 2027, most likely.

TSMC gave some early estimates compared to the coming N2P process, where A16 is expected to improve performance by 8-10 percent at the same voltage and complexity or reduce power by 15-20 percent at the same frequency and transistor count.

The big innovation in the A16 generation will be backside power delivery, something TSMC calls “Super Power Rail.” This runs a network for power distribution on the back side of the silicon wafer, connected to the transistors through little tunnels through it. This improves density and potentially reliability, as power doesn’t have to be routed around with all the signal and clock distribution lines on the top side of the chip. Other chip manufacturers are pursuing similar technologies (Intel’s PowerVia comes to mind)—basically different approaches to the same idea.

TSMC

TSMC

TSMC

TSMC may be a little later than competitors like Intel with this kind of technology, as it has been pushed back a little. It was originally expected to debut in the N2P process, and now will be first introduced in A16 instead.

Chips in Apple products that use the A16 process will be able to have even more stuff (more cores, bigger caches) than the N2 process while maintaining the same power profile.

Having chips with more density or a better power profile earlier than others is one of Apple’s big advantages, but the real magic comes from excellent chip design and software development that optimizes Apple’s software specifically for the chips they produce.